This invention relates to a dual-port memory device with RAM(Random Access Memory) and SAM(Serial Access Memory) ports, more particularly, a dual-port memory device also comprises a redundant circuit. The dual-port memory device has one or more RAM and SAM ports formed of memory cell array blocks, respectively. The dual-port memory device has been developed to be used as a VRAM(Video RAM) for graphic display.
In a conventional DRAM(Dynamic RAM), when a data is transferred from a processor to a peripheral device, the data is transferred to a memory and subsequently the peripheral device carries out the access of the transferred data. In that case, the processor can't transfer the data to the memory during the access is carried out by the peripheral device.
But, in the dual-port memory, the peripheral device carries out the access of the transferred data in the memory through a second port, while the data is transferred to the memory through a first port. The first and the second ports represent the RAM and the SAM ports, respectively. The SAM port has a fast access time so a VRAM is used for the high resolution and the high speed graphic display. In order to carry out the split transfer of this dual-port memory device, a normal memory means is divided into upper and lower parts.
When the lower part is a first normal memory and the upper part is a second normal memory, the SAM of the second normal memory carries out a read transfer operation RT or a write transfer operation WT while the SAM of the first normal memory carries out a read operation or a write operation. Further, the redundant circuit prevents the reduction of the production yield due to the defect of the normal memory means caused by integration. Therefore, if the defect is generated at a certain part of the normal memory means, the redundant circuit is connected instead of the defective normal memory means in order to maintain the normal operation.
In order to carry out the split transfer mode in the conventional dual-port memory device with the redundant circuit means, the normal memory means is divided into the first and the second memories, where the read or the write operation is carried out at one part while the RT or the WT operation is carried out at the other part. Thus, a first or a second transfer signal is required correspondingly to the first and the second normal memories for the split transfer of the normal memory means.
In that case, a first and second redundant circuit are also provided to the redundant memory means respectively in the same manner with the normal memory means, so that the first and the second redundant circuits of the redundant memory means are connected instead of the first and the second normal memories when the normal memory means have the defect, thereby the normal operation is maintained on.
There is, however, a disadvantage that the size of the memory device must be enlarged, since the redundant memory means should be provided with the first and the second redundant circuits respectively for the compensation of the defects of the first and the second normal memories in the split transfer mode.